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LPC2468FBD208芯片解密特性的简介

  深圳市深圳芯片解密研究所专业提供芯片解密、IC解密、单片机破解等解密服务,曾多次获得客户的好评,以科学继续与专业服务赢得了客户的信任。以下是LPC2468FBD208芯片解密特性的简介,仅供参考。
  · ARM7TDMI-S processor, running at up to 72 MHz.
  · 512 kB on-chip flash program memory with In-System Programming (ISP) and In-Application Programming (IAP) capabilities. Flash program memory is on the ARM local bus for high performance CPU access.
  · 98 kB on-chip SRAM includes:
     - 64 kB of SRAM on the ARM local bus for high performance CPU access.
     - 16 kB SRAM for Ethernet interface. Can also be used as general purpose SRAM.
     - 16 kB SRAM for general purpose DMA use also accessible by the USB.
     - 2 kB SRAM data storage powered from the Real-Time Clock (RTC) power domain.
  · Dual Advanced High-performance Bus (AHB) system allows simultaneous Ethernet DMA, USB DMA, and program execution from on-chip flash with no contention.
  · EMC provides support for asynchronous static memory devices such as RAM, ROM and flash, as well as dynamic memories such as Single Data Rate SDRAM.
  · Advanced Vectored Interrupt Controller (VIC), supporting up to 32 vectored interrupts.
  · General Purpose AHB DMA controller (GPDMA) that can be used with the SSP, I2S-bus, and SD/MMC interface as well as for memory-to-memory transfers.
  · Serial Interfaces:
     - Ethernet MAC with MII/RMII interface and associated DMA controller. These functions reside on an independent AHB bus.
     - USB 2.0 full-speed dual port Device/Host/OTG Controller with on-chip PHY and associated DMA controller.
     - Four UARTs with fractional baud rate generation, one with modem control I/O, one with IrDA support, all with FIFO.
     - CAN controller with two channels.
     - SPI controller.
     - Two SSP controllers, with FIFO and multi-protocol capabilities. One is an alternate for the SPI port, sharing its interrupt. SSPs can be used with the GPDMA controller.
     - Three I2C-bus interfaces (one with open-drain and two with standard port pins).
     - I2S (Inter-IC Sound) interface for digital audio input or output. It can be used with the GPDMA.
  · Other peripherals:
     - SD/MMC memory card interface.
     - 160 General purpose I/O pins with configurable pull-up/down resistors.
     - 10-bit ADC with input multiplexing among 8 pins.
     - 10-bit DAC.
     - Four general purpose timers/counters with 8 capture inputs and 10 compare outputs. Each timer block has an external count input.
     - Two PWM/timer blocks with support for three-phase motor control. Each PWM has an external count inputs.
     - RTC with separate power domain, clock source can be the RTC oscillator or the APB clock.
     - 2 kB SRAM powered from the RTC power pin, allowing data to be stored when the rest of the chip is powered off.
     - WatchDog Timer (WDT). The WDT can be clocked from the internal RC oscillator, the RTC oscillator, or the APB clock.
  · Standard ARM test/debug interface for compatibility with existing tools.
  · Emulation trace module supports real-time trace.
  · Single 3.3 V power supply (3.0 V to 3.6 V).
  · Three reduced power modes: idle, sleep, and power-down.
  · Four external interrupt inputs configurable as edge/level sensitive. All pins on PORT0 and PORT2 can be used as edge sensitive interrupt sources.
  · Processor wake-up from Power-down mode via any interrupt able to operate during Power-down mode (includes external interrupts, RTC interrupt, USB activity, Ethernet wake-up interrupt, CAN bus activity, PORT0/2 pin interrupt).
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